1. Field of the Invention
The present invention relates to a data processor that carries out processing while accessing the memory and a method thereof, particularly to a data processor and data processing method directed to reduce power consumption during memory access.
2. Description of the Background Art
The processing speed of microprocessors has increased drastically these few years. The clock frequency of microprocessors and the frequency of the microprocessor accessing the memory have increased correspondingly. The data processor incorporating such a microprocessor is prone to consume more power.
In order to increase the operating period of time for data processors that operate by battery such as portable information apparatuses, the technology of reducing the power consumption of the entire data processor is now indispensable.
In many cases, the conventional data processor employs a SRAM (Static Random Access Memory) and a DRAM (Dynamic Random Access Memory) as the memory incorporated therein. Particularly in the case of the SRAM having the unitary circuit storing information of 1 bit constituted by flip flop circuits formed mainly of CMOS (Complementary Metal Oxide Semiconductor) circuits, power consumption of the SRAM will increase when the data to be stored in a memory element is inverted during the data writing mode.
Many conventional data processors have the memory such as the SRAM connected directly to the data bus. Data is written randomly into the memory, causing the data stored in the memory element to be altered frequently. Thus, there was a problem that the power consumption could not be suppressed.